Conventionally, an LSI is formed by integrating elements in a two-dimensional plane on a silicon substrate. Generally, a storage capacity of memory is increased by reducing dimensions of (miniaturizing) an element. However, in recent years, even this miniaturization is becoming difficult in terms of cost and technology. Improvements in photolithographic technology are necessary for miniaturization, but costs required in lithographic processes are rapidly increasing. In addition, even if miniaturization is achieved, it is expected that physical limitations such as those of withstand voltage between elements are encountered, unless the drive voltage and so on are scaled. Moreover, the reduction in distance between memory elements that accompanies miniaturization causes an increase in adverse effects due to capacitive coupling between each of the memory elements during operations. In other words, there is a high possibility that operation as a device becomes difficult. Accordingly, in recent years, there are proposed many nonvolatile semiconductor memory devices (stacking-type nonvolatile semiconductor memory devices) in which memory cells are disposed three-dimensionally in order to increase a degree of integration of memory.
One conventional semiconductor memory device in which memory cells are disposed three-dimensionally uses a transistor with a cylindrical column type structure. The semiconductor memory device using the transistor with a cylindrical column type structure is provided with multiple layers of polysilicon configuring a gate electrode, and a pillar-shaped columnar semiconductor. The columnar semiconductor is disposed to penetrate the polysilicon layers and has a memory cell formed at portions of intersection with those polysilicon layers. In this memory cell, the columnar semiconductor functions as a channel (body) portion of a transistor. A vicinity of the columnar semiconductor is provided with a charge storage layer, each sandwiching a tunnel insulating layer and configured to store a charge. Furthermore, a block insulating layer is formed in a vicinity of the charge storage layer. The polysilicon, columnar semiconductor, tunnel insulating layer, charge storage layer and block insulating layer configured in this manner form a memory string of series-connected memory cells.
An erase operation in this kind of conventional semiconductor memory device in which memory cells are disposed three-dimensionally is performed in units of a memory block, the memory block being an assembly of memory strings to which word lines are commonly connected. In a conventional stacking-type semiconductor memory device, there is a problem that, along with an increase in the number of layers, there is an increase in the number of word lines commonly connected to a plurality of memory strings in one memory block, this leading to an increase in the number of memory cells included in one memory block. Consequently, there is desired a stacking-type semiconductor memory device which, in addition to being capable of the erase operation on a memory block basis, is also capable of an erase operation to selectively erase only a part of the memory cells in a memory block.